Nanoanalysis of Electrochemical Processes

StacIE aims to scale up the stack production on the level of cell components by development of industrial processes, improvement of profitability of cell design by reducing complexity and optimizing manufacturing technique of the porous transport layer (PTL) and bipolar plate (BPP). For PTL and BPP alternative materials and substrate coating methods are identified and developed further. Additionally, an increase in performance and lifetime is aimed for. Fabrication techniques for a direct coating of the catalyst layer onto the porous transport layer is developed and investigated, overcoming the challenge to optimize the structure of the PTL to the catalyst layer. Also, accelerated stress tests are developed and the degradation mechanisms unraveled. Thorough structural elucidation completes the picture.

Two-dimensional materials show enormous potential concerning application in electronic devices because of their extraordinary properties. The utilization of materials of this kind, however, is accompanied by significant challenges as layer-dependent properties substantially determine potential device functionalities. These challenges are caused by an extensive lack of systematic studies investigating fabrication processes of electronic devices, including optimization, as well as resulting electrical functionalities considering number of layers and anisotropy. Studies of this kind are intrinsically complex and defying as non-destructive methods for determining the number of layers of 2D materials integrated in electronic devices have to be combined and tuned with layer-dependent measurements of electrical properties. Within the framework of this proposal the influence of the number of layers on device properties of electronic devices based on the 2D material black phosphorous will be distinctly determined by a methodical combination of analytical-reflectance spectroscopy and measurements of the electronic transport. For this purpose, various device architectures will be investigated with respect to their layer-dependent properties and anisotropy. These properties include both purely electronical and valleytronical aspects. The number of layers is ascertained by a custom-built optical method which exploits the properties of the spectral reflectance of the material. For varying device architectures various approaches like lateral and vertical contacting, different gate dielectrics, tunneling contacts as well as different surface passivations are utilized. As operating principle for fundamental and electrical characterization, field effect, Hall effect and valley-Hall effect are exploited. Obtained insights will contribute to a fundamental comprehension of properties of 2D materials with respect to their applicability in modern and future-based electronics.